Exact rational frequency translation using a phase locked loop (PLL) is well known. However, it has generally been implemented with integer dividers yielding an output/input frequency ratio given by: FOUT/FIN=B/A (A and B are both integers). The integer constraint significantly limits the useful range of ratios, because FOUT is bounded by the range of the PLL's internal frequency source (typically a VCO). The bound on FOUT limits the usefulness of the B/A integer divide ratios. A further constraint on the usefulness of this approach is that FIN/A must be sufficiently large to ensure that the input PLL phase margin is not compromised due to an excessively low PFD update rate. Generally, it is desirable to have the A and B dividers be programmable in order to support a range of FOUT/FIN ratios. A problem arises, however, when the A and/or B dividers lack sufficient depth to satisfy a particular FOUT/FIN ratio.
Accordingly, there is a need in the art for a frequency translator that can perform a wide range of conversion ratios and, in particular, such a translator that can perform frequency conversion according to non-integral ratios.